Hierarchical fault tolerance memory architecture with 3-dimension interconnect

This paper proposed hierarchical fault tolerance techniques for ultrahigh-density memories based on 3- dimension interconnect technology. It describes how to implement hierarchical architecture with different granularity redundancies and how to combine error correction code (ECC), built-in self-test (BIST), built-in repair-analysis (BIRA), and built-in self-repair (BISR) capabilities. Simulation is employed to estimate the memory behavior of various configurations, and experimental results indicate that the proposed method has substantial reliability improvements over conventional techniques. For a memory with 1% bit-level failure rate and 50% device-level defect density, the proposed method can gain 100% reliability by using less than 30% extra overhead. It proves the availability of the proposed architecture.