A built-in self-test and self-diagnosis scheme for embedded SRAM

Author

Wang, Chih-Wea ; Wu, Chi-Feng ; Li, Jin-Fu ; Wu, Cheng-Wen ; Teng, Tony ; Chiu, Kevin ; Lin, Hsiao-Ping

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2000

fDate

2000

Firstpage

45

Lastpage

50

Abstract

Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault diagnosis system for embedded SRAM. It supports manufacturing test as well as diagnosis for design verification and yield improvement. The proposed BISD circuit is on-line programmable for its March test algorithms. Test chips have been designed and implemented. Our experimental results show that the BISD hardware overhead is about 2.4% for a typical 128 Kb SRAM and only 0.65% for a 2 Mb SRAM

Keywords

SRAM chips; built-in self test; fault diagnosis; built-in self-test; embedded SRAM; fault diagnosis; memory test; self-diagnosis scheme; system-on-chip; Bandwidth; Built-in self-test; Circuit faults; Fault diagnosis; Hardware; Logic testing; Pins; Random access memory; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian

Conference_Location

Taipei

ISSN

1081-7735

Print_ISBN

0-7695-0887-1

Type

conf

DOI

10.1109/ATS.2000.893601

Filename

893601