Run-time reconfigurable power-aware pipelined signed array multiplier design

Signed multipliers are widely used in computer arithmetic units. For signed multiplier in a specific length using 2´s complement number representation, operands with shorter lengths than the multiplier cannot be calculated unless using sign extension. These extended sign bits will cause waste power dissipation and delay when at least one of the operands is negative. Sign extension also severely degrades the power awareness of the multiplier. To make the multiplier run-time reconfigurable and improve its power awareness, a selective design method to design pipelined signed array multiplier is proposed in this paper. Along with the 2-D pipeline gating technique, the designed reconfigurable multipliers are able to process operands in any length without sign extension. These designs also have very good power awareness as well as latency reduction to the changing of input precision. Results show 65% power saving and 44% latency reduction for a 16-bit multiplier under equal input precision probabilities.