A 5-bit 1 Gsample/s two-stage ADC with a new flash folded architecture

Author

Huang, Hung-Yu ; Lin, Ying-Zu ; Chang, Soon-Jyh

Author_Institution

Nat. Cheng Kung Univ., Tainan

fYear

2007

fDate

Oct. 30 2007-Nov. 2 2007

Firstpage

1

Lastpage

4

Abstract

A 5-bit 1 GSample/s two-stage ADC is designed and simulated in TSMC 0.18-mum CMOS technology. The new architecture combines the characteristics of flash, subranging and folding ADC. The analog front-end of this work is the same as that of a typical flash ADC. By replacing folding amplifier with the current-mode multiplexer (MUX), cyclic thermometer code, the digital output of folding ADC, is obtained and frequency multiplication effect is avoided. Besides, the slow switching of the reference voltage range is also avoided. The number of the comparators is reduced to 16, and it is 32 typically. Operating at 1 GSample/s, the ENOB is 4.92 and 4.71 bit at input frequency 10 and 500 MHz, respectively. This ADC consumes 63 mW from a 1.8 V supply, achieving FOMs of 2.4 pJ/conversion-step at 1 GSample/s.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); cyclic codes; multiplexing equipment; thermometers; MUX; TSMC 0.18-mum CMOS technology; analogue-to-digital converter; comparators; current-mode multiplexer; cyclic thermometer code; flash folded architecture; frequency 10 MHz; frequency 500 MHz; frequency multiplication effect; power 63 mW; size 0.18 mum; two-stage ADC; voltage 1.8 V; word length 4.71 bit; word length 4.92 bit; word length 5 bit; Bandwidth; CMOS technology; Clocks; Frequency conversion; Multiplexing; Optical amplifiers; Parallel architectures; Preamplifiers; Quantization; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 2007 - 2007 IEEE Region 10 Conference

Conference_Location

Taipei

Print_ISBN

978-1-4244-1272-3

Electronic_ISBN

978-1-4244-1272-3

Type

conf

DOI

10.1109/TENCON.2007.4428897

Filename

4428897