• DocumentCode
    2752185
  • Title

    Efficient built-in self-test algorithm for memory

  • Author

    Wang, Sying-Jyan ; Wei, Chen-Jung

  • Author_Institution
    Inst. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung, Taiwan
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    66
  • Lastpage
    70
  • Abstract
    We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are needed for the detection of coupling faults. As a result, the number of test patterns required is less than half of the traditional method, while the extra hardware is negligible
  • Keywords
    DRAM chips; built-in self test; BIST; DRAM; built-in self-test algorithm; coupling faults; pseudorandom testing; test patterns; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Computer science; Fault detection; Hardware; Logic; Random access memory; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
  • Conference_Location
    Taipei
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-0887-1
  • Type

    conf

  • DOI
    10.1109/ATS.2000.893604
  • Filename
    893604
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2752185