Top-down-based timing-driven steiner tree construction with wire sizing and buffer insertion

Given a set of connecting nodes in a signal net, based on the concept of sharing-buffer insertion and hidden Steiner- point assignment and the result of optimal wire width and buffer insertion in a wire segment (J.T. Yan, 2006) a top-down-based merging approach is proposed to construct a timing-driven rectilinear Steiner tree with wire sizing and buffer insertion The experimental results show that our proposed merging approach without wire sizing and buffer insertion reduces 5%~39% timing delay than the MVERT approach[5] in reasonable CPU time. Besides that, the proposed approach with wire sizing and buffer insertion reduces 28%~76% timing delay than that without wire sizing and buffer insertion for the tested signal nets.