Electrostatic integrity and performance enhancement for UTB InGaAs-OI MOSFET with high-k dielectric through spacer design

The impact of spacer design on the electrostatic integrity (EI) and performance of Ultra-Thin-Body (UTB) InGaAs-OI MOSFETs with various high-k dielectrics are analyzed. With fixed EOT and Ioff, performance and EI degrade as gate dielectric constant (k) increases. Compared with nitride spacer, UTB InGaAs-OI MOSFET with vacuum spacer can mitigate the EI and performance degradations due to thicker physical layer of high-k dielectric. UTB InGaAs-OI MOSFET with high-k dielectric (k ≥ 18) and vacuum spacer shows larger Ion, smaller DIBL and subthreshold swing than that with nitride spacer. With fixed EOT, using gate-to-source/drain underlap can suppress the performance degradation as gate dielectric constant increases. For UTB InGaAs-OI MOSFET with underlap design, using nitride spacer may improve its gate control of channel potential and show better performance than vacuum spacer.