Testability analysis and ATPG on behavioral RT-level VHDL

Author

Corno, Fulvio ; Prinetto, Paolo ; Reorda, Matteo Sonza

Author_Institution

Dipt. di Autom. e Inf., Politecnico di Torino, Italy

fYear

1997

fDate

1-6 Nov 1997

Firstpage

753

Lastpage

759

Abstract

This paper proposes an environment to address testability analysis and test pattern generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties. The approach, being based on an abstract representation, is particularly suited for large circuits, where gate-level ATPGs are often inefficient

Keywords

automatic testing; fault diagnosis; hardware description languages; integrated circuit testing; logic testing; ATPG; abstract representation; behavioral RT-level VHDL; fault coverage properties; fault model; final gate-level fault coverage; large circuits; test patterns; testability analysis; Algorithm design and analysis; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit synthesis; Circuit testing; Genetic algorithms; Hardware design languages; Pattern analysis; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1997. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-4209-7

Type

conf

DOI

10.1109/TEST.1997.639688

Filename

639688