DocumentCode
2752567
Title
Fast hierarchical test path construction for DFT-free controller-datapath circuits
Author
Makris, Yiorgos ; Collins, Jamison ; Orailoglu, Alex
Author_Institution
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
fYear
2000
fDate
2000
Firstpage
185
Lastpage
190
Abstract
We discuss a hierarchical test generation method for DFT-free controller-datapath pairs. A transparency based scheme is devised for the datapath, wherein locally generated vectors are translated into global design test. The controller is examined through influence tables, used to generate valid control state sequences for testing each module through hierarchical test paths. Fault coverage levels and vector counts thus attained match closely, those of traditional test generation methodologies, while sharply reducing the corresponding computational cost
Keywords
automatic test pattern generation; logic testing; ATPG; DFT-free controller-datapath circuits; computational cost reduction; fast hierarchical test path construction; fault coverage levels; global design test; influence tables; locally generated vectors; module testing; test generation; transparency based scheme; valid control state sequences; vector counts; Adders; Automatic generation control; Circuit faults; Circuit testing; Computational efficiency; Costs; Feedback loop; Hardware; Performance analysis; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location
Taipei
ISSN
1081-7735
Print_ISBN
0-7695-0887-1
Type
conf
DOI
10.1109/ATS.2000.893623
Filename
893623
Link To Document