Title :
Faster processing for microprocessor functional ATPG
Author :
Hirase, Junichi ; Yoshimura, Shinichi
Author_Institution :
Matsushita Electr. Ind. Co. Ltd., Japan
Abstract :
In order to improve the quality of microprocessor tests, the use of instruction sets for testing is indispensable. This paper discusses how fault coverage can be improved with a short test pattern that repeatedly samples an R number of instructions as L sets from an S number of instructions and selects from amongst these L sets those for which the fault coverage can be improved. Continuing, it argues that the processing speed can be increased by selecting a certain number of sets containing an R number of instructions from an S number of instructions. This approach proved effective in tests using software created on these principles
Keywords :
automatic test pattern generation; identification; instruction sets; integrated circuit testing; logic testing; microprocessor chips; fault coverage improvement; functional testing; instruction sets; microprocessor functional ATPG; microprocessor tests; processing speed increase; short test pattern; test pattern generation; Automatic test pattern generation; Automatic testing; Design for testability; Fault detection; Fault location; Instruction sets; Large scale integration; Microprocessors; Test pattern generators; Voltage;
Conference_Titel :
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location :
Taipei
Print_ISBN :
0-7695-0887-1
DOI :
10.1109/ATS.2000.893624
