Detection of SRAM cell stability by lowering array supply voltage

Author

Kwai, Ding-Ming ; Chang, Hung-Wen ; Liao, Hung-Jen ; Chiao, Ching-Hua ; Chou, Yung-Fa

Author_Institution

Taiwan Semicond. Manuf. Co., Taiwan

fYear

2000

fDate

2000

Firstpage

268

Lastpage

273

Abstract

In this paper, we discuss a design-for-test technique for the detection of cell stability in static random access memory (SRAM). The power supply to the memory array is isolated and independently accessible from an external terminal. By lowering the array supply voltage, the cell stability is degraded, making the defective cells susceptible to noises induced by read/write operations. On-silicon characterization result using 0.18 μm CMOS technology is reported. It shows that the weak tailing bits in the statistical distribution can manifest themselves. The implementation of the test mode is inherently low-cost and can be combined with previously proposed methods for an improved detection capability

Keywords

CMOS memory circuits; SRAM chips; circuit stability; design for testability; integrated circuit testing; logic testing; 0.18 micron; CMOS technology; DFT technique; SRAM cell stability detection; array supply voltage reduction; design-for-test technique; detection capability; memory array; static random access memory; test mode; CMOS technology; Degradation; Design for testability; Isolation technology; Power supplies; Random access memory; SRAM chips; Stability; Statistical distributions; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian

Conference_Location

Taipei

ISSN

1081-7735

Print_ISBN

0-7695-0887-1

Type

conf

DOI

10.1109/ATS.2000.893636

Filename

893636