A 2.38-mW 93.22-dB SNR third-order switched capacitor feedforward delta sigma ADC

A third-order switched capacitor delta sigma ADC is implemented in SMIC 0.18-μm CMOS technology for low frequency applications. By adopting feedforward architecture, the loop stability can be improved, and the output swing of integrators can be suppressed significantly, thus improving the linearity. In order to provide stable operation for the modulator, oscillation detecting circuit is employed to detect the occurrence of overload. Modulator is realized with fully-differential switched capacitor, utilizing a single-loop single-bit output topology. Decimation filter is completed with a fourth-order comb filter. This delta sigma ADC achieves a signal-to-noise ratio of 93.22-dB over a bandwidth of 1-kHz, corresponding to a resolution of 15.2-bits. The chip shows a good linearity, and the measured power dissipation is 2.38-mW under 2.5-V analog power supply and 1.8-V digital power supply.