DocumentCode :
2752842
Title :
Memory test time reduction by interconnecting test items
Author :
Wu, Wen-Jer ; Tang, Chuan Yi
Author_Institution :
Cadence Design Syst., Hsin-Chu, Taiwan
fYear :
2000
fDate :
2000
Firstpage :
290
Lastpage :
298
Abstract :
The idea is to interconnect test items to reuse memory states left from the previous test item for saving initialization and verification sequences. Meanwhile, signal settling time of the tester between two consecutive test items being applied can also be minimized since all test items are connected together into a continuous one. The interconnection problem is transformed to the Rural Chinese Postman (RCP) problem. The RCP problem is a famous NP-hard problem, one way to solve the RCP problem is by modeling as an integer linear programming (ILP) model. However, in the worst case, it will incur an exponential number of constraints; therefore, it is not suitable for practical usage. Instead of putting all constraints at once, we generate and solve a number of successive ILP models with the smaller number of constraints. The total numbers of iterations and constraints applied to solve ILP models are analyzed and compared
Keywords :
graph theory; integer programming; integrated circuit testing; integrated memory circuits; linear programming; NP-hard problem; constraints; initialization sequences; integer linear programming model; interconnection problem; iterations; memory test time reduction; rural Chinese postman problem; signal settling time; successive ILP models; test items interconnection; verification sequences; Computer science; Fault detection; Integer linear programming; Performance evaluation; Production; Protocols; Research and development; Testing; Timing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location :
Taipei
ISSN :
1081-7735
Print_ISBN :
0-7695-0887-1
Type :
conf
DOI :
10.1109/ATS.2000.893639
Filename :
893639
Link To Document :
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