Title :
Memory reduction of IDDQ test compaction for internal and external bridging faults
Author :
Maeda, Toshiyuki ; Kinoshita, Kozo
Author_Institution :
Dept. of Appl. Phys., Osaka Univ., Japan
Abstract :
IDDQ testing is an effective method for bridging faults of CMOS circuits. Since the measurement of current in IDDQ testing takes a long time, a short test sequence is strongly desirable for reducing test application time. In this paper we present a test compaction method for an IDDQ test sequence using a reassignment method for all bridging faults in sequential circuits. Since a large memory space is required to treat all bridging faults, an effective fault list is required. We propose the test compaction method using an assignment list of signal values. The proposed method is realized with small size memory and runs fast for many large sequential circuits. Experimental results on the benchmark circuits show that it is effective in reducing test length for given weighted random sequences
Keywords :
CMOS logic circuits; automatic testing; fault simulation; integrated circuit testing; logic testing; sequential circuits; CMOS circuits; IDDQ test compaction; IDDQ test sequence; external bridging faults; internal bridging faults; memory reduction; reassignment method; sequential circuits; test application time reduction; weighted random sequences; Benchmark testing; CMOS memory circuits; Circuit faults; Circuit testing; Compaction; Current measurement; Random sequences; Sequential analysis; Sequential circuits; Time measurement;
Conference_Titel :
Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian
Conference_Location :
Taipei
Print_ISBN :
0-7695-0887-1
DOI :
10.1109/ATS.2000.893648
