Cyclic greedy generation method for limited number of IDDQ tests

Author

Shinogi, Tsuyoshi ; Ushio, Masahiro ; Hayashi, Terumine

Author_Institution

Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan

fYear

2000

fDate

2000

Firstpage

362

Lastpage

366

Abstract

This paper proposes a generation method (called Cyclic Greedy generation method) of IDDQ test sets for maximizing the number of detected faults under the constraint that the number of test patterns is limited. First this method greedily generates the given limited number of test patterns, then it greedily re-generates each pattern sequentially all over again and again in a cyclic manner. Each test pattern is generated by the iterative improvement method of random patterns. The experimental results show that the number of undetected faults remained by the Cyclic Greedy generation method is 13% less than by the pure greedy generation method in average for the large ISCAS85&89 circuits

Keywords

CMOS integrated circuits; electric current measurement; fault diagnosis; integrated circuit testing; iterative methods; CMOS IC; IDDQ tests; ISCAS85&89 circuits; cyclic; cyclic greedy generation method; iterative method; random patterns; short circuit faults; test patterns; undetected faults; CMOS logic circuits; Circuit faults; Circuit testing; Electrical fault detection; Electronic equipment testing; Fault detection; Logic testing; Random number generation; Sequential analysis; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian

Conference_Location

Taipei

ISSN

1081-7735

Print_ISBN

0-7695-0887-1

Type

conf

DOI

10.1109/ATS.2000.893650

Filename

893650