Effective parallel processing techniques for the generation of test data for a logic built-in self test system

Logic Built-in Self rest (LBIST) is a test methodology adopted by some companies to test their complex processor designs. It can involve a very high volume of simulation, perhaps up to one to two million patterns. For large designs, the simulation time (which includes logic simulation, random stimulus generation and signature computations) can be enormous. Parallel processing provides a relief for this long simulation time. This paper describes a technique to efficiently partition patterns among different processors. These patterns are derived from on-product Pseudo-Random Pattern Generators (PRPGs) and the signature is a serial compression of the response data from all of the patterns. Both the PRPG and signature calculation have a serial pattern dependency, which normally would prohibit parallel simulation of the patterns. We show how to quickly advance a PRPG state to jump ahead to any specific pattern´s starting state and an innovative post processing technique to compute correct signatures from initially incorrect ones computed in parallel among different processes. The results demonstrate that the overhead to correct the signatures is small and the parallel speed up is very effective