Design for sequential testability: an internal state reseeding approach for 100 % fault coverage

Author

Flottes, M.L. ; Landrault, C. ; Petitqueux, A.

Author_Institution

Lab. d´´Inf. de Robotique et de Microelectron., Montpellier, France

fYear

2000

fDate

2000

Firstpage

404

Lastpage

409

Abstract

This paper proposes a method to select observation points and flip-flops for partial reset. The method does not target minimum DFT insertion but a maximum improvement on testability. The proposed non-scan approach allows a at-speed testing. Experimental results show that the method achieves 100% fault coverage and 100% fault efficiency for benchmark circuits while requiring less ATPG effort (CPU time) with no scan necessity

Keywords

automatic test pattern generation; controllability; design for testability; fault diagnosis; logic design; logic testing; observability; sequential circuits; 100 percent; ATPG; CPU time; at-speed testing; benchmark circuits; controllability; fault coverage; fault efficiency; flip-flops; internal state reseeding; minimum DFT insertion; non-scan approach; observation points; partial reset; sequential testability; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Controllability; Costs; Flip-flops; Observability; Sequential analysis; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian

Conference_Location

Taipei

ISSN

1081-7735

Print_ISBN

0-7695-0887-1

Type

conf

DOI

10.1109/ATS.2000.893657

Filename

893657