DocumentCode
275343
Title
The combination of scheduling, allocation, and mapping in a single algorithm
Author
Cloutier, Richard J. ; Thomas, Donald E.
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear
1990
fDate
24-28 Jun 1990
Firstpage
71
Lastpage
76
Abstract
A single high-level synthesis algorithm is presented that schedules the operations of a data dependence graph, allocates the necessary hardware and maps the operations to specific functional units. This is achieved by extending the global analysis approach developed for force-directed scheduling to include individual module instances. This new algorithm should be applicable to any behavioral synthesis system that schedules operations from a data dependence graph
Keywords
VLSI; circuit CAD; circuit layout CAD; scheduling; behavioral synthesis system; data dependence graph; force-directed scheduling; functional units; global analysis; high-level synthesis algorithm; Algorithm design and analysis; Contracts; Costs; Data engineering; Hardware; High level languages; High level synthesis; Iterative algorithms; Processor scheduling; Scheduling algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location
Orlando, FL
ISSN
0738-100X
Print_ISBN
0-89791-363-9
Type
conf
DOI
10.1109/DAC.1990.114832
Filename
114832
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