An adaptive timing-driven layout for high speed VLSI

Author

Sutanthavibul, Suphachai ; Shragowitz, Eugene

Author_Institution

Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA

fYear

1990

fDate

24-28 Jun 1990

Firstpage

Lastpage

Abstract

An adaptive timing-driven VLSI layout system, called JUNE, has been developed. The constructive algorithm, which combines placement with the global routing, constructs a placement satisfying timing and routability constraints. The placement problem for each macro is solved hierarchically as a sequence of two optimization problems followed by an adaptive correction procedure. Experimental results for industrial sea-of-gates chips confirmed the effectiveness of this approach

Keywords

VLSI; circuit layout CAD; JUNE; adaptive correction procedure; adaptive timing-driven layout; constructive algorithm; effectiveness; global routing; high speed VLSI; optimization; placement; routability constraints; sea-of-gates chips; Algorithm design and analysis; Circuits; Clocks; Delay; Iterative algorithms; Iterative methods; Logic design; Routing; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

Conference_Location

Orlando, FL

ISSN

0738-100X

Print_ISBN

0-89791-363-9

Type

conf

DOI

10.1109/DAC.1990.114835

Filename

114835

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=275346