Title :
A new min-cut placement algorithm for timing assurance layout design meeting net length constraint
Author :
Terai, Masayuki ; Takahashi, Kazuhiro ; Sato, Koji
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A new VLSI min-cut placement algorithm is presented for timing assurance layout design. When critical nets are given net length constraints, the proposed algorithm can place cells so that the constraints may be met. This algorithm is built into the layout system for gate arrays, called GALOP. The application results are described for the case of clock skew control of an ECL 12K-gate array
Keywords :
VLSI; circuit layout CAD; emitter-coupled logic; logic arrays; ECL 12K-gate array; GALOP; min-cut placement algorithm; net length constraint; timing assurance layout design; Algorithm design and analysis; Automatic control; Clocks; Delay; Routing; Signal design; Timing; Upper bound; Weight control; Wire;
Conference_Titel :
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
0-89791-363-9
DOI :
10.1109/DAC.1990.114836
