Timing verification using HDTV

Author

Martello, Alan R. ; Levitan, Steven P. ; Chiarulli, Donald M.

Author_Institution

Pittsburgh Univ., PA, USA

fYear

1990

fDate

24-28 Jun 1990

Firstpage

118

Lastpage

123

Abstract

A system designed for verifying the consistency of timing specifications for digital circuits is presented. The utility of the system comes from the need to verify that existing digital components will interact correctly when placed together in a system. To perform this interface verification, two operators are defined which allow one to perform useful reasoning concerning the interface. One operator deals with causality and another with timing constraints. The system can also be used in the case of verifying specifications of unimplemented components. The system is implemented as a hardware design timing verification (HDTV) program

Keywords

circuit CAD; circuit analysis computing; digital integrated circuits; integrated circuit testing; logic testing; HDTV; causality; digital circuits; hardware design timing verification; timing constraints; timing specifications; timing verification; Circuit synthesis; Circuit testing; Digital circuits; HDTV; Hardware; Integrated circuit interconnections; Logic gates; Sequential circuits; System testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

Conference_Location

Orlando, FL

ISSN

0738-100X

Print_ISBN

0-89791-363-9

Type

conf

DOI

10.1109/DAC.1990.114840

Filename

114840