Title :
A novel approach to reduce interconnect complexity in ANN hardware implementation
Author :
Brunelli, Luiz ; Melcher, Elmar U K ; De Brito, Alisson V. ; Freire, Raimundo C S
Author_Institution :
Departamento de Engenharia Eletrica, Univ. Fed. de Campina Grande, Brazil
fDate :
31 July-4 Aug. 2005
Abstract :
Hardware implementation of large digital artificial neural networks is limited by several constraints, such as the complexity of neural interconnections. This paper presents a novel approach to solve the interconnection problem for artificial neural networks, using reconfigurable computing and dynamically reconfigured FPGAs in a new computational way: the execution patterns (EPs). The EPs allow reducing the influence of interconnections through the removal of data transport via busses. Thus, data transport is not necessary to perform the computation and interconnection complexity between neurons is reduced.
Keywords :
field programmable gate arrays; interconnections; neural nets; reconfigurable architectures; system buses; ANN hardware; FPGA; digital artificial neural network; execution pattern; interconnect complexity; neural interconnection; reconfigurable computing; Artificial neural networks; Bars; Computer networks; Data analysis; Field programmable gate arrays; Function approximation; Integrated circuit interconnections; Neural network hardware; Neurons; Pattern recognition;
Conference_Titel :
Neural Networks, 2005. IJCNN '05. Proceedings. 2005 IEEE International Joint Conference on
Print_ISBN :
0-7803-9048-2
DOI :
10.1109/IJCNN.2005.1556379
