Title :
An optimal algorithm for floorplan area optimization
Author :
Wang, Ting-Chi ; Wong, D.F.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Abstract :
An optimal algorithm for the VLSI floorplan area optimization problem is presented. The algorithm is an extension of the technique described by L. Stockmeyer (Information and Control, vol.59, p.91-101, 1983). Experimental results indicate that this algorithm pruned a very large number of redundant implementations. In addition, since the algorithm basically exploits the geometric property of the topology of the given floorplan it does not need to depend on the polar dual graphs to calculate the longest paths. Consequently it is able to run more efficiently than the branch-and-bound algorithm
Keywords :
VLSI; circuit layout CAD; computational geometry; VLSI floorplan area optimization; geometric property; optimal algorithm; topology; Algorithm design and analysis; Circuit topology; Costs; Integrated circuit interconnections; Performance evaluation; Polynomials; Radio access networks; Very large scale integration; Wheels;
Conference_Titel :
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
0-89791-363-9
DOI :
10.1109/DAC.1990.114851
