Pad placement and ring routing for custom chip layout

Author

Wang, Deborah C.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1990

fDate

24-28 Jun 1990

Firstpage

193

Lastpage

199

Abstract

An optimum scheme is presented for interconnecting the chip core and the I/O pads in the final stage of physical design. The pad placement routing, based on linear assignment, determines the dimension of the pad ring and selects the optimum position for each pad with the objective of minimizing the chip area and the total wire length. The router is based on a channel-routing algorithm which incorporates additional features to address the special needs of the ring configuration. It attempts to achieve 100% routing completion in a rectangular ring-shaped area with two interconnect layers. The complete package has been implemented as part of the BEAR Layout System for custom chip design

Keywords

circuit layout CAD; BEAR Layout System; I/O pads; channel-routing algorithm; chip area; chip core; custom chip layout; interconnect layers; linear assignment; optimum position; pad placement routing; pad ring dimension; rectangular ring-shaped area; ring configuration; ring routing; wire length; Assembly systems; Atherosclerosis; Chip scale packaging; Conductors; Laboratories; Logic design; Rivers; Routing; Terminology; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE

Conference_Location

Orlando, FL

ISSN

0738-100X

Print_ISBN

0-89791-363-9

Type

conf

DOI

10.1109/DAC.1990.114853

Filename

114853