Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits

Recently developed necessary and sufficient conditions for robust path-delay-fault testability are applied to develop synthesis procedures which produce two-level and multilevel circuits with high degrees of robust path delay fault testability. For circuits which can be flattened to two levels, a covering procedure is given which optimizes for robust path delay fault testability. These two-level circuits can then be algebraically factored to produce robustly path-delay-fault testable multilevel circuits. For regular structures which cannot be flattened to two levels, a composition procedure is given which allows for the construction of robustly path-delay-fault testable regular structures. Finally, it is shown how these two techniques can be combined to produce cascaded combinational logic blocks that are robustly path-delay-fault testable. These techniques are demonstrated on a variety of examples. It is possible to produce entire clips that are fully path delay testable using these techniques