• DocumentCode
    2753637
  • Title

    New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults

  • Author

    Van de Goor, Ad J. ; Hamdioui, Said ; Gaydadjiev, Georgi N. ; AL-Ars, Zaid

  • Author_Institution
    ComTex, Gouda, Netherlands
  • fYear
    2009
  • fDate
    23-26 Nov. 2009
  • Firstpage
    391
  • Lastpage
    396
  • Abstract
    Due to the rapid decrease of technology feature size speed related faults, such as Address Decoder Delay Faults (ADDFs), are becoming very important. In addition, increased leakage currents demand for improved tests for Bit Line Imbalance Faults (BLIFs)(caused by memory cell pass transistor leakage). This paper contributes to new and improved algorithms for detecting these faults. First it provides an improved version of existing GalPat algorithm and introduces two new algorithms to detect ADDFs; the paper also shines a new light on the use of the different stress combinations (counting methods, data-backgrounds) and their importance for the detection of ADDFs. Second, it provides an improved algorithm for detecting BLIFs; it increases the defect coverage by being able to detect lower leakage currents.
  • Keywords
    decoding; delays; fault diagnosis; integrated circuit testing; leakage currents; logic circuits; logic gates; ADDF; BLIF; NAND gate; address decoder delay faults; bit line imbalance faults; counting methods; data backgrounds; fault detection; leakage currents; memory cell pass transistor leakage; Added delay; Collision mitigation; Decoding; Fault detection; Laboratories; Leak detection; Leakage current; Legged locomotion; Stress; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Asian Test Symposium, 2009. ATS '09.
  • Conference_Location
    Taichung
  • ISSN
    1081-7735
  • Print_ISBN
    978-0-7695-3864-8
  • Type

    conf

  • DOI
    10.1109/ATS.2009.87
  • Filename
    5359299