Title :
Design of repairable and fully diagnosable folded PLAs for yield enhancement
Author :
Wey, Chin-Long ; Ding, Jyhyeung ; Chang, Tsin-Yuan
Author_Institution :
Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA
Abstract :
A fault-tolerant design of repairable and fully diagnosable folded PLA is presented, in which the defects can be repaired without reconfiguring the external routing. The design achieves a full diagnosability of single and multiple stuck-at, bridging, and crosspoint faults, and leads to a significant yield improvement. The physical layout and floor plan are also provided to assess the chip area
Keywords :
circuit layout CAD; logic CAD; logic arrays; logic testing; bridging; crosspoint faults; fault-tolerant design; floor plan; full diagnosability; fully diagnosable folded PLAs; physical layout; repairable PLA; stuck-at faults; yield enhancement; Circuit faults; Circuit testing; Fault tolerance; Integrated circuit yield; Logic design; Manufacturing processes; Probes; Programmable logic arrays; Routing; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
0-89791-363-9
DOI :
10.1109/DAC.1990.114875
