• DocumentCode
    275380
  • Title

    Layout compaction with attractive and repulsive constraints

  • Author

    Onozawa, Akira

  • Author_Institution
    NTT LSI Lab., Kanagawa, Japan
  • fYear
    1990
  • fDate
    24-28 Jun 1990
  • Firstpage
    369
  • Lastpage
    374
  • Abstract
    A one-dimensional VLSI layout compaction algorithm with attractive and repulsive constraints is proposed. Depending on these constraints, the proposed algorithm shrinks [expands] the spaces among the specified layout elements without causing any design rule violations. The resultant layout has less cross-talks and delay. The proposed network simplex algorithm experimentally proves to be efficient in both time and space
  • Keywords
    VLSI; circuit layout CAD; delays; attractive constraints; cross-talks; delay; network simplex algorithm; one-dimensional VLSI layout compaction algorithm; repulsive constraints; Algorithm design and analysis; Circuit optimization; Compaction; Delay; Design automation; Design optimization; Laboratories; Large scale integration; Very large scale integration; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
  • Conference_Location
    Orlando, FL
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-363-9
  • Type

    conf

  • DOI
    10.1109/DAC.1990.114885
  • Filename
    114885
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=275380