Title :
Layout compaction with attractive and repulsive constraints
Author_Institution :
NTT LSI Lab., Kanagawa, Japan
Abstract :
A one-dimensional VLSI layout compaction algorithm with attractive and repulsive constraints is proposed. Depending on these constraints, the proposed algorithm shrinks [expands] the spaces among the specified layout elements without causing any design rule violations. The resultant layout has less cross-talks and delay. The proposed network simplex algorithm experimentally proves to be efficient in both time and space
Keywords :
VLSI; circuit layout CAD; delays; attractive constraints; cross-talks; delay; network simplex algorithm; one-dimensional VLSI layout compaction algorithm; repulsive constraints; Algorithm design and analysis; Circuit optimization; Compaction; Delay; Design automation; Design optimization; Laboratories; Large scale integration; Very large scale integration; Wire;
Conference_Titel :
Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
Conference_Location :
Orlando, FL
Print_ISBN :
0-89791-363-9
DOI :
10.1109/DAC.1990.114885
