• DocumentCode
    275381
  • Title

    Datapath generator based on gate-level symbolic layout

  • Author

    Matsumoto, Nobu ; Watanabe, Yoko ; Usami, Kimiyoshi ; Sugeno, Yukio ; Hatada, Hiroshi ; Mori, Shojiro

  • Author_Institution
    Toshiba Corp., Kawasaki, Japan
  • fYear
    1990
  • fDate
    24-28 Jun 1990
  • Firstpage
    388
  • Lastpage
    393
  • Abstract
    A data-path generator that generates high-density LSI mask layouts equivalent to hand-crafted ones is described. An entry of the generator is a hierarchical symbolic layout at the gate level. The bit-and-row-slicing technique is a key feature for realizing large-size and high-density data-path generation. A 21 K-transistor data-path whose density is 5.64 KTr/mm2, greater than the 5.38 KTr/mm2 of a hand-crafted datapath, was generated using 1-μm CMOS technology
  • Keywords
    CMOS integrated circuits; circuit layout CAD; large scale integration; 1 micron; CMOS technology; LSI mask layouts; bit-and-row-slicing technique; data-path generator; gate-level symbolic layout; CMOS logic circuits; CMOS technology; Compaction; Delay; Design automation; Large scale integration; Large-scale systems; Libraries; Microelectronics; Semiconductor devices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE
  • Conference_Location
    Orlando, FL
  • ISSN
    0738-100X
  • Print_ISBN
    0-89791-363-9
  • Type

    conf

  • DOI
    10.1109/DAC.1990.114888
  • Filename
    114888
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=275381