An object-oriented VHDL design environment

A system-level design environment (SDE) for the VHSIC hardware description language (VHDL) is presented. The object-oriented approach is used for modeling the VHDL entities, design constraints, and even design patterns. The data model and its internal schema, which are suitable for the VHDL semantics, are proposed. SDE allows a designer to reconfigure the designed schematic by binding its generic components to technology-specific ones. It is effectively used for version control. SDE verifies the design by dynamically checking the constraints. The standard VHDL is extended in order to represent the constraints properly