Constraint generation for routing analog circuits

An approach for generating constraints on interconnect parasitics to drive the routing of analog circuits is presented. The approach involves (a) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the router while meeting the performance constraints, and (b) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information on differential circuits. A prototype constraint generator is described. It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits