Corolla based circuit partitioning and resynthesis

Application of corolla-based partitioning to improve synthesis of large multi-level logic circuits is introduced. First, stem regions, petals, and corollas are defined. Next, the partitioning algorithm is outlined and the resynthesis process is described. Results of partitioning and logic resynthesis on a variety of large circuit benchmarks are summarized. It is found that logic resynthesis based on corolla partitioning consistently reduces reconvergent fanout branches, transistor pairs and layout areas, while improving circuit delay and testability