DocumentCode :
2754169
Title :
Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption
Author :
Kundu, Subhadip ; Kumar S, K. ; Chattopadhyay, Santanu
Author_Institution :
Dept. of Electron. & Electr. Commun., Indian Inst. of Technol., Kharagpur, India
fYear :
2009
fDate :
23-26 Nov. 2009
Firstpage :
307
Lastpage :
312
Abstract :
Test mode power dissipation has been found to be much more than the functional power dissipation. Since dynamic power dissipation had a major contribution to the heat generated, most of the studies focused on reducing the transitions during testing. But at submicron technology, leakage current becomes significantly high. This demands a control on the leakage current as well. In this work, we propose techniques to simultaneously reduce the switching activity and keeping the leakage current under check. The overall average switching activity reduction is 70.01% and reduction in leakage power is about 6.31%, the maximum being 99.33% in switching and 9.92% in leakage.
Keywords :
CMOS integrated circuits; automatic test pattern generation; integrated circuit testing; leakage currents; switching; CMOS technology; automated test pattern generation; dynamic power consumption; leakage current; leakage power consumption; switching activity; test mode power dissipation; test pattern customization; test pattern selection; CMOS technology; Circuit testing; Clocks; Electronic equipment testing; Energy consumption; Leakage current; Power dissipation; Power generation; Switching circuits; Timing; ATPG; Dynamic power; Leakage power; Scan cell; Vector reordering;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asian Test Symposium, 2009. ATS '09.
Conference_Location :
Taichung
ISSN :
1081-7735
Print_ISBN :
978-0-7695-3864-8
Type :
conf
DOI :
10.1109/ATS.2009.35
Filename :
5359327
Link To Document :
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