Title :
System and architecture optimizations for low power MPEG-1 video decoding
Author :
Molloy, S. ; Jain, R.
Author_Institution :
Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA
Abstract :
Providing MPEG-1 video decoding capability in a low power device requires optimizations at the circuit, architecture, and system levels. In this paper several architecture and system level optimizations are described that allow the decoding of unmodified MPEG-1 bitstreams at CIF resolutions with significantly lower power. These techniques can be used together with a reduced supply voltage to provide MPEG-1 video capability in a battery-powered multimedia device.
Keywords :
decoding; CIF resolutions; architecture optimization; battery-powered multimedia device; low power MPEG-1 video decoding; low power device; supply voltage reduction; system level optimization; Circuits; Consumer electronics; Decoding; Discrete cosine transforms; Energy consumption; Filters; Frequency; Laboratories; Random access memory; Voltage;
Conference_Titel :
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-1953-2
DOI :
10.1109/LPE.1994.573191
