Title :
Power and performance simulator: ESP and its application for 100 MIPS/W class RISC design
Author :
Sato, T. ; Nagamatsu, M. ; Tago, H.
Author_Institution :
Toshiba Res. & Dev. Centre, Kawasaki, Japan
Abstract :
A new power and performance simulator, ESP (Early design Stage Power) is presented. With ESP, it becomes possible to do more precise optimization between power and performance in an early design stage. We applied it to a low-power RISC design and proved it useful for lower power design.
Keywords :
reduced instruction set computing; 100 MIPS; ESP; LSI; RISC design; circuit optimization; microprocessor design; performance simulator; power simulator; Clocks; Design engineering; Electrostatic precipitators; Microprocessors; Pipelines; Power engineering and energy; Radio frequency; Reduced instruction set computing; Research and development; Semiconductor devices;
Conference_Titel :
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-1953-2
DOI :
10.1109/LPE.1994.573197
