Title :
A high-level synthesis methodology for low-power VLSI design
Author :
Goodby, L. ; Orailoglu, A. ; Chau, P.M.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
A high-level synthesis methodology for low-power design is described. With the objective of supporting the design of low-power, performance-constrained systems such as signal processing applications, the methodology enables the designer to place throughput and latency constraints on the synthesized design. A library-based design style is used, where libraries may include multiple implementations of each component type. Library components are characterized by their relative power, area, and delay performance. The methodology has been implemented in the Sierra high-level synthesis system.
Keywords :
high level synthesis; Sierra; area performance; delay performance; high-level synthesis methodology; latency constraints; library-based design style; low-power VLSI design; multiple implementations; performance-constrained systems; relative power; signal processing applications; throughput constraints; Delay; Energy consumption; High level synthesis; Libraries; Logic design; Pipeline processing; Throughput; Timing; Very large scale integration; Voltage;
Conference_Titel :
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-1953-2
DOI :
10.1109/LPE.1994.573198
