Title :
High level testability analysis using VHDL Automatic Test Pattern Generation
Author :
Giamarchi, F. ; Capocchi, L. ; Federici, D. ; Bisgambiglia, P.A.
Author_Institution :
SPE UMR CNRS 6134 Lab., Univ. of Corsica, Corte
Abstract :
This paper is about problems of testability of circuits. In account of the progress achieved in the field of integration, we are in presence of increasingly complex circuits. So to pose the problem of testability and maintenance, from the phase of the circuit design is the means more adapted in order to improve them and make it possible to carry out the test at a reasonable cost. In this article we present an automatic test pattern generator using discrete event modeling methodology for the simulation of behavioral faults of VHDL, called ATPG-DEVS.
Keywords :
VLSI; automatic test pattern generation; discrete event simulation; fault simulation; hardware description languages; integrated circuit design; integrated circuit modelling; integrated circuit testing; ATPG-DEVS; VHDL automatic test pattern generation; VLSI circuits; behavioral faults simulation; circuit design; circuits testability; complex circuits; discrete event modeling methodology; high level testability analysis; maintenance problem; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Costs; Discrete event simulation; Pattern analysis; Test pattern generators; DEVS; VHDL; test; test pattern;
Conference_Titel :
Electrotechnical Conference, 2008. MELECON 2008. The 14th IEEE Mediterranean
Conference_Location :
Ajaccio
Print_ISBN :
978-1-4244-1632-5
Electronic_ISBN :
978-1-4244-1633-2
DOI :
10.1109/MELCON.2008.4618436
