DocumentCode
2754423
Title
Modest power savings for applications dominated by switching of large capacitive loads
Author
Hahm, M.
Author_Institution
Dept. of Electr. Eng., Rochester Univ., NY, USA
fYear
1994
fDate
10-12 Oct. 1994
Firstpage
60
Lastpage
61
Abstract
A method for improving the power efficiency of conventional CMOS through charge storage and reuse is proposed and evaluated. The application of the method is specific to nodes within a circuit which are dominated by capacitive loads much larger than the gate capacitance of a minimum-sized device within the desired CMOS technology. An upper bound on power savings via the proposed method is given, and implementation and shortcomings of the method are discussed.
Keywords
CMOS logic circuits; CMOS logic circuits; CMOS technology; charge reuse; charge storage; large capacitive load switching; minimum-sized device; power efficiency; power savings; CMOS logic circuits; CMOS technology; Capacitance; Capacitors; Energy consumption; Logic devices; Logic gates; Power supplies; Switching frequency; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics, 1994. Digest of Technical Papers., IEEE Symposium
Conference_Location
San Diego, CA, USA
Print_ISBN
0-7803-1953-2
Type
conf
DOI
10.1109/LPE.1994.573203
Filename
573203
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