Design and evaluation of reduced self-capacitance inductor for fast-switching SiC BJT dc/dc converters

The paper presents design, measurements and evaluation of the inductor with reduced self-capacitance. As an reference inductor with the same parameters but non-optimized self-capacitance is chosen. Differences in the parasitic capacitance of the inductor are validated by four measurement methods and experimentally confirmed on a 2 kW, 100 kHz dc/dc converter with silicon carbide BJTs. When the low-capacitance inductor is applied the switching performance is better, especially high-frequency resonances are limited. Additionally, it was found that the power losses were reduced by approximately 20%.