DocumentCode
2754656
Title
Performance evaluation of parallel applications on multiprocessor systems on chip
Author
Hammami, O. ; Tian, G.
Author_Institution
ENSTA, Paris
fYear
2008
fDate
5-7 May 2008
Firstpage
305
Lastpage
309
Abstract
A MPSOC based on Network-on-Chip (NoC) is developed and presented. Some matrix applications are developed for this platform according to the shared-memory programming model. Performance results are compared between the NoC based multiprocessor system and the traditional bus-based MPSOC. The concerns of efficient data distribution and requisition for the memory system have also been considered in this paper. A conclusion is made in the end showing the apparent advantages brought in by the NoC based MPSOC.
Keywords
distributed shared memory systems; integrated circuit interconnections; multiprocessor interconnection networks; network-on-chip; data distribution; multiprocessor systems-on-chip; network-on-chip; shared-memory programming model; Computational modeling; Computer architecture; Field programmable gate arrays; Libraries; Multiprocessing systems; Network-on-a-chip; Packaging machines; Parallel programming; Semiconductor device measurement; System-on-a-chip; MPSOC; NoC; Parallel programming; Performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrotechnical Conference, 2008. MELECON 2008. The 14th IEEE Mediterranean
Conference_Location
Ajaccio
Print_ISBN
978-1-4244-1632-5
Electronic_ISBN
978-1-4244-1633-2
Type
conf
DOI
10.1109/MELCON.2008.4618452
Filename
4618452
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