Title :
Power reduction techniques for digital array multipliers
Author :
Moshnyaga, Vasily G.
Author_Institution :
Fukuoka Univ., Fukuoka
fDate :
Oct. 30 2007-Nov. 2 2007
Abstract :
Low-power multipliers are very important for reducing energy consumption of digital processing systems. This paper discusses recent techniques proposed for low power array multipliers and presents their experimental comparison on 16x16 bit multiplier design.
Keywords :
low-power electronics; multiplying circuits; digital array multipliers; digital processing systems; energy consumption; low power multipliers; power reduction techniques; Adders; CMOS digital integrated circuits; CMOS technology; Computer science; Delay; Design optimization; Energy consumption; Power engineering and energy; Signal design; Voltage;
Conference_Titel :
TENCON 2007 - 2007 IEEE Region 10 Conference
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-1272-3
Electronic_ISBN :
978-1-4244-1272-3
DOI :
10.1109/TENCON.2007.4429037
