Title :
Design of a VLSI neural network arrhythmia classifier
Author :
Shawkey, H. ; Elsimary, H. ; Haddara, H. ; Ragaie, H.F.
Author_Institution :
Dept. of Electron. Res. Inst. Microelectron., Ain Shams Univ., Cairo, Egypt
Abstract :
Artificial neural networks are now attractive tools to enhance and improve the efficiency, the capability and the features of instrumentation in applications related to measurements, system identification, and control. The aim of this paper is to implement an implantable cardiverter defibrillator (ICD) using an analog neural network. The paper describes a VLSI neural network chip to be implemented using 1.2 μm CMOS technology, which acts as an intracardiac tachycardia classification system. A robust neural network is less sensitive to noise, drift and offsets inherent in analog applications. The proposed classifier uses two types of neural networks a Kohonen self organizing map (KSOM) circuit and a winner take all (WTA) circuit
Keywords :
CMOS analogue integrated circuits; VLSI; biomedical equipment; biomedical measurement; defibrillators; electrocardiography; medical signal processing; neural chips; patient monitoring; prosthetics; self-organising feature maps; signal classification; 1.2 micron; CMOS technology; Kohonen self organizing map circuit; VLSI neural network arrhythmia classifier; VLSI neural network chip; analog neural network design; artificial neural networks; implantable cardioverter defibrillator; instrumentation; intracardiac tachycardia classification system; measurements; system control; system identification; winner take all circuit; Artificial neural networks; CMOS technology; Circuits; Control systems; Instruments; Neural networks; Paper technology; Semiconductor device measurement; System identification; Very large scale integration;
Conference_Titel :
Radio Science Conference, 1999. NRSC '99. Proceedings of the Sixteenth National
Conference_Location :
Cairo
Print_ISBN :
977-5031-62-1
DOI :
10.1109/NRSC.1999.760911
