Title :
Analogue CMOS DSSS CDLL synchronisation scheme employing complex spreading sequences
Author :
Elenjical, Tinu Sabu ; Linde, Louis ; Sinha, Saurabh
Author_Institution :
Nokia Siemens Networks, Midrand
Abstract :
A DSSS system is a radio frequency (RF) communication system in which the baseband information signal is intentionally spread over a large bandwidth by modulating the signal with a spreading sequence before it is modulated onto a carrier. This baseband information signal can only be recovered if both carrier and spreading sequence recovery is implemented in the receiver. Spreading sequence recovery is performed by the delay-lock loop. This paper describes the design of an analogue 2.4 GHz direct sequence spread spectrum (DSSS) complex delay-lock loop (CDLL) architecture that is implemented using the Austria Microsystems (AMS) 0.35 mum complementary metal-oxide semi-conductor (CMOS) process. The CDLL is implemented using a single rail power supply of 3.3 V and it has a power consumption of 140 mW.
Keywords :
CMOS analogue integrated circuits; UHF integrated circuits; delay lock loops; spread spectrum communication; synchronisation; Austria microsystems; CDLL synchronisation scheme; CMOS analogue circuit; DSSS; complex delay-lock loop; direct sequence spread spectrum; frequency 2.4 GHz; power 140 mW; radio frequency communication system; size 0.35 mum; voltage 3.3 V; Bandwidth; Baseband; CMOS process; Delay; Frequency synchronization; Power supplies; RF signals; Radio frequency; Rails; Spread spectrum communication; Analogue complex delay-lock loop; Pseudonoise coded communication; analogue decision directed coherent Costas recovery loop; complex spreading sequences;
Conference_Titel :
Electrotechnical Conference, 2008. MELECON 2008. The 14th IEEE Mediterranean
Conference_Location :
Ajaccio
Print_ISBN :
978-1-4244-1632-5
Electronic_ISBN :
978-1-4244-1633-2
DOI :
10.1109/MELCON.2008.4618464
