DocumentCode
2755082
Title
Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test
Author
Chung, Chen-I ; Jhou, Jyun-Sian ; Cheng, Ching-Hwa ; Li, Sih-Yan
Author_Institution
Dept. of Electron. Eng., Feng-Chia Univ., Taichung, Taiwan
fYear
2009
fDate
23-26 Nov. 2009
Firstpage
163
Lastpage
168
Abstract
The self wide-range (26%~76%), fine-scale (34 ps) duty cycle adjustment technique with high-precision (28 ps) calibration circuit are proposed for at-speed delay test and performance binning. Test chip DFT strategies are validated fully function work by instruments and HOY wireless test system.
Keywords
built-in self test; calibration; design for testability; HOY wireless test system; calibration mechanism; fine-scale duty cycle adjustment technique; functional built-in delay binning; high-precision calibration circuit; on-chip at-speed self test; test chip DFT strategies; Automatic testing; Calibration; Circuit faults; Circuit testing; Clocks; Delay effects; Delay estimation; Electronic equipment testing; Flip-flops; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Test Symposium, 2009. ATS '09.
Conference_Location
Taichung
ISSN
1081-7735
Print_ISBN
978-0-7695-3864-8
Type
conf
DOI
10.1109/ATS.2009.72
Filename
5359370
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