The implementation of hardware subroutines on field programmable gate arrays

The dynamically reconfigurable Plessey ERA (electrically reconfigurable array), by supporting the paging of full and partial sets of configuration data at system clock speed, allows silicon multitasking and introduces the concept of the hardware subroutine. The ERA requires 2.5 times less data per equivalent gate as compared to the established industry standard devices. In addition, loading the data in parallel bytes at clock speeds up to 25 MHz reduces the time taken for the complete configuration of a 10000 equivalent gate array to less than 140 μs