The Use of UML Sequence Diagram for System-on-Chip System Level Transaction-based Functional Verification

An important problem faced by system-on-chip transaction-based verification is how to design the complex transaction test sequence. Scenario-based sequence diagram is a good way to capture the system level functional specification. In the paper, we propose a method to support transaction level verification of SoC based on UML sequence diagram. We use UML sequence diagram to capture the communication and collaboration behaviour among IP cores in system-on-chip and build high level specification for transaction level verification. Then these sequence diagrams will be used to guide the generation of transaction test sequence. We develop a component-based transaction verification environment named SoC-CBTVE. In the SoC-CBTVE, based on the method, we verify a typical SoC design. Experimental results show that UML sequence diagram can capture the complex communication behaviour among IP cores in SoC design, and efficiently supports SoC system level functional verification