model order reduction for RLC interconnects using response dependent condensation

The continuous improvement in the performance and increase in the sizes of VLSI systems make electrical interconnect and package (EIP) design and modeling increasingly more important. Special software tools must be used for the design of high-performance VLSI systems. Furthermore, larger and faster systems require larger and more accurate circuit models. The model order reduction techniques are used for modeling such systems. This paper presents an efficient model order reduction method for large linear VLSI circuits using response-dependent condensation. Experimental results show that the effectiveness of the proposed technique. Significant reduction in computational expense is achieved as the size of the reduced equations is much less than that of the original system.