Parallel implementation of image classifier architectures using transputer arrays

This paper considers fundamental issues with respect to a particular type of classifier architecture (based on a cellular array of logical processors forming a memory network) and investigates and assesses experimentally the relationship between the internal structure of the classifier and the implementational infrastructure realised in terms of a transputer array. The memory network pattern classifier architecture based on binary feature (e.g. pixel level) sampling consists of an array of memory cells for each possible pattern class, each cell associated with a feature which is related to an ordered pixel grouping in an input pattern. Such systems offer flexible, easily implemented and relatively low cost solutions to a variety of tasks involving image recognition