Genetic algorithm based NoC design with voltage/frequency islands

Due to increasing complexity of the embedded applications, designing a Network-on-Chip (NoC) architecture under energy, cost, and performance constraints has become challenging issue. Especially, energy management and clock distribution stand in the center of NoC synthesis flow. NoC communication infrastructure allows us to design globally asynchronous locally synchronous (GALS) systems, which suits well for energy minimization and clock speed control. In this paper, we present a genetic algorithm based method that maps the tasks of the given application onto two different voltage/frequency islands (VFIs) to minimize the total energy consumption of the system. We compared the proposed method with the one that does not consider VFI. Our experiments on several benchmarks show that VFI based method brings up to 37% energy reduction under given timing constraint.