• DocumentCode
    2756022
  • Title

    A Novel Seed Selection Algorithm for Test Time Reduction in BIST

  • Author

    Chakraborty, Rupsa ; Chowdhury, Dipanwita Roy

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
  • fYear
    2009
  • fDate
    23-26 Nov. 2009
  • Firstpage
    15
  • Lastpage
    20
  • Abstract
    The seed (initial state) of a pseudo-random pattern generator (PRPG) for built-in self-test (BIST), significantly influences the fault coverage and total test application time. This paper introduces a one-pass seed selection algorithm, for any known PRPG. Due to its single-pass nature, unlike the state-of-the-art exhaustive search methods, the proposed algorithm is more time and memory efficient. Experimental results on ISCAS´85 and ISCAS´89 benchmark circuits, and synthetic SoCs built out of the combinational benchmarks, show considerable reduction in test length within comparable fault efficiencies, almost 100%, with respect to the existing methods.
  • Keywords
    automatic test pattern generation; built-in self test; integrated circuit testing; logic testing; random sequences; system-on-chip; BIST; benchmark circuits; built-in self-test; combinational benchmarks; fault coverage; one-pass seed selection algorithm; pseudorandom pattern generator; synthetic SoC; test application time; test time reduction; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Computer science; Electrical fault detection; Fault detection; Logic testing; Test pattern generators; Seed selection; built-in self-test; cellular automata; pseudo-random pattern generation; test length;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Asian Test Symposium, 2009. ATS '09.
  • Conference_Location
    Taichung
  • ISSN
    1081-7735
  • Print_ISBN
    978-0-7695-3864-8
  • Type

    conf

  • DOI
    10.1109/ATS.2009.10
  • Filename
    5359422